avx512cd.rs - source
Description: Source of the Rust file `library/core/src/../../stdarch/crates/core_arch/src/x86/avx512cd.rs`.

#
core/stdarch/crates/core_arch/src/x86/
avx512cd.rs

    1use crate::core_arch::{simd::*, x86::*};
    2use crate::intrinsics::simd::*;
    3
    4#[cfg(test)]
    5use stdarch_test::assert_instr;
    6
    7/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
    8///
    9/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmw_epi32&expand=553)
    10#[inline]
    11#[target_feature(enable = "avx512cd")]
    12#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    13#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
    14#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    15pub const fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i {
    16    _mm512_set1_epi32(k as i32)
    17}
    18
    19/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
    20///
    21/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmw_epi32&expand=552)
    22#[inline]
    23#[target_feature(enable = "avx512cd,avx512vl")]
    24#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    25#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
    26#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    27pub const fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i {
    28    _mm256_set1_epi32(k as i32)
    29}
    30
    31/// Broadcast the low 16-bits from input mask k to all 32-bit elements of dst.
    32///
    33/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmw_epi32&expand=551)
    34#[inline]
    35#[target_feature(enable = "avx512cd,avx512vl")]
    36#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    37#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d
    38#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    39pub const fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i {
    40    _mm_set1_epi32(k as i32)
    41}
    42
    43/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
    44///
    45/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmb_epi64&expand=550)
    46#[inline]
    47#[target_feature(enable = "avx512cd")]
    48#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    49#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
    50#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    51pub const fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i {
    52    _mm512_set1_epi64(k as i64)
    53}
    54
    55/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
    56///
    57/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmb_epi64&expand=549)
    58#[inline]
    59#[target_feature(enable = "avx512cd,avx512vl")]
    60#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    61#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
    62#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    63pub const fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i {
    64    _mm256_set1_epi64x(k as i64)
    65}
    66
    67/// Broadcast the low 8-bits from input mask k to all 64-bit elements of dst.
    68///
    69/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmb_epi64&expand=548)
    70#[inline]
    71#[target_feature(enable = "avx512cd,avx512vl")]
    72#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    73#[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q
    74#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    75pub const fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i {
    76    _mm_set1_epi64x(k as i64)
    77}
    78
    79/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
    80///
    81/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi32&expand=1248)
    82#[inline]
    83#[target_feature(enable = "avx512cd")]
    84#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    85#[cfg_attr(test, assert_instr(vpconflictd))]
    86pub fn _mm512_conflict_epi32(a: __m512i) -> __m512i {
    87    unsafe { transmute(vpconflictd(a.as_i32x16())) }
    88}
    89
    90/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    91///
    92/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi32&expand=1249)
    93#[inline]
    94#[target_feature(enable = "avx512cd")]
    95#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    96#[cfg_attr(test, assert_instr(vpconflictd))]
    97pub fn _mm512_mask_conflict_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
    98    unsafe {
    99        let conflict = _mm512_conflict_epi32(a).as_i32x16();
    100        transmute(simd_select_bitmask(k, conflict, src.as_i32x16()))
    101    }
    102}
    103
    104/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    105///
    106/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi32&expand=1250)
    107#[inline]
    108#[target_feature(enable = "avx512cd")]
    109#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    110#[cfg_attr(test, assert_instr(vpconflictd))]
    111pub fn _mm512_maskz_conflict_epi32(k: __mmask16, a: __m512i) -> __m512i {
    112    unsafe {
    113        let conflict = _mm512_conflict_epi32(a).as_i32x16();
    114        transmute(simd_select_bitmask(k, conflict, i32x16::ZERO))
    115    }
    116}
    117
    118/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
    119///
    120/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi32&expand=1245)
    121#[inline]
    122#[target_feature(enable = "avx512cd,avx512vl")]
    123#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    124#[cfg_attr(test, assert_instr(vpconflictd))]
    125pub fn _mm256_conflict_epi32(a: __m256i) -> __m256i {
    126    unsafe { transmute(vpconflictd256(a.as_i32x8())) }
    127}
    128
    129/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    130///
    131/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi32&expand=1246)
    132#[inline]
    133#[target_feature(enable = "avx512cd,avx512vl")]
    134#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    135#[cfg_attr(test, assert_instr(vpconflictd))]
    136pub fn _mm256_mask_conflict_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
    137    unsafe {
    138        let conflict = _mm256_conflict_epi32(a).as_i32x8();
    139        transmute(simd_select_bitmask(k, conflict, src.as_i32x8()))
    140    }
    141}
    142
    143/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    144///
    145/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi32&expand=1247)
    146#[inline]
    147#[target_feature(enable = "avx512cd,avx512vl")]
    148#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    149#[cfg_attr(test, assert_instr(vpconflictd))]
    150pub fn _mm256_maskz_conflict_epi32(k: __mmask8, a: __m256i) -> __m256i {
    151    unsafe {
    152        let conflict = _mm256_conflict_epi32(a).as_i32x8();
    153        transmute(simd_select_bitmask(k, conflict, i32x8::ZERO))
    154    }
    155}
    156
    157/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
    158///
    159/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi32&expand=1242)
    160#[inline]
    161#[target_feature(enable = "avx512cd,avx512vl")]
    162#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    163#[cfg_attr(test, assert_instr(vpconflictd))]
    164pub fn _mm_conflict_epi32(a: __m128i) -> __m128i {
    165    unsafe { transmute(vpconflictd128(a.as_i32x4())) }
    166}
    167
    168/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    169///
    170/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi32&expand=1243)
    171#[inline]
    172#[target_feature(enable = "avx512cd,avx512vl")]
    173#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    174#[cfg_attr(test, assert_instr(vpconflictd))]
    175pub fn _mm_mask_conflict_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
    176    unsafe {
    177        let conflict = _mm_conflict_epi32(a).as_i32x4();
    178        transmute(simd_select_bitmask(k, conflict, src.as_i32x4()))
    179    }
    180}
    181
    182/// Test each 32-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    183///
    184/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi32&expand=1244)
    185#[inline]
    186#[target_feature(enable = "avx512cd,avx512vl")]
    187#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    188#[cfg_attr(test, assert_instr(vpconflictd))]
    189pub fn _mm_maskz_conflict_epi32(k: __mmask8, a: __m128i) -> __m128i {
    190    unsafe {
    191        let conflict = _mm_conflict_epi32(a).as_i32x4();
    192        transmute(simd_select_bitmask(k, conflict, i32x4::ZERO))
    193    }
    194}
    195
    196/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
    197///
    198/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi64&expand=1257)
    199#[inline]
    200#[target_feature(enable = "avx512cd")]
    201#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    202#[cfg_attr(test, assert_instr(vpconflictq))]
    203pub fn _mm512_conflict_epi64(a: __m512i) -> __m512i {
    204    unsafe { transmute(vpconflictq(a.as_i64x8())) }
    205}
    206
    207/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    208///
    209/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi64&expand=1258)
    210#[inline]
    211#[target_feature(enable = "avx512cd")]
    212#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    213#[cfg_attr(test, assert_instr(vpconflictq))]
    214pub fn _mm512_mask_conflict_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
    215    unsafe {
    216        let conflict = _mm512_conflict_epi64(a).as_i64x8();
    217        transmute(simd_select_bitmask(k, conflict, src.as_i64x8()))
    218    }
    219}
    220
    221/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    222///
    223/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi64&expand=1259)
    224#[inline]
    225#[target_feature(enable = "avx512cd")]
    226#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    227#[cfg_attr(test, assert_instr(vpconflictq))]
    228pub fn _mm512_maskz_conflict_epi64(k: __mmask8, a: __m512i) -> __m512i {
    229    unsafe {
    230        let conflict = _mm512_conflict_epi64(a).as_i64x8();
    231        transmute(simd_select_bitmask(k, conflict, i64x8::ZERO))
    232    }
    233}
    234
    235/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
    236///
    237/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi64&expand=1254)
    238#[inline]
    239#[target_feature(enable = "avx512cd,avx512vl")]
    240#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    241#[cfg_attr(test, assert_instr(vpconflictq))]
    242pub fn _mm256_conflict_epi64(a: __m256i) -> __m256i {
    243    unsafe { transmute(vpconflictq256(a.as_i64x4())) }
    244}
    245
    246/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    247///
    248/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi64&expand=1255)
    249#[inline]
    250#[target_feature(enable = "avx512cd,avx512vl")]
    251#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    252#[cfg_attr(test, assert_instr(vpconflictq))]
    253pub fn _mm256_mask_conflict_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
    254    unsafe {
    255        let conflict = _mm256_conflict_epi64(a).as_i64x4();
    256        transmute(simd_select_bitmask(k, conflict, src.as_i64x4()))
    257    }
    258}
    259
    260/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    261///
    262/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi64&expand=1256)
    263#[inline]
    264#[target_feature(enable = "avx512cd,avx512vl")]
    265#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    266#[cfg_attr(test, assert_instr(vpconflictq))]
    267pub fn _mm256_maskz_conflict_epi64(k: __mmask8, a: __m256i) -> __m256i {
    268    unsafe {
    269        let conflict = _mm256_conflict_epi64(a).as_i64x4();
    270        transmute(simd_select_bitmask(k, conflict, i64x4::ZERO))
    271    }
    272}
    273
    274/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit. Each element's comparison forms a zero extended bit vector in dst.
    275///
    276/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi64&expand=1251)
    277#[inline]
    278#[target_feature(enable = "avx512cd,avx512vl")]
    279#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    280#[cfg_attr(test, assert_instr(vpconflictq))]
    281pub fn _mm_conflict_epi64(a: __m128i) -> __m128i {
    282    unsafe { transmute(vpconflictq128(a.as_i64x2())) }
    283}
    284
    285/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using writemask k (elements are copied from src when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    286///
    287/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi64&expand=1252)
    288#[inline]
    289#[target_feature(enable = "avx512cd,avx512vl")]
    290#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    291#[cfg_attr(test, assert_instr(vpconflictq))]
    292pub fn _mm_mask_conflict_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
    293    unsafe {
    294        let conflict = _mm_conflict_epi64(a).as_i64x2();
    295        transmute(simd_select_bitmask(k, conflict, src.as_i64x2()))
    296    }
    297}
    298
    299/// Test each 64-bit element of a for equality with all other elements in a closer to the least significant bit using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in dst.
    300///
    301/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi64&expand=1253)
    302#[inline]
    303#[target_feature(enable = "avx512cd,avx512vl")]
    304#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    305#[cfg_attr(test, assert_instr(vpconflictq))]
    306pub fn _mm_maskz_conflict_epi64(k: __mmask8, a: __m128i) -> __m128i {
    307    unsafe {
    308        let conflict = _mm_conflict_epi64(a).as_i64x2();
    309        transmute(simd_select_bitmask(k, conflict, i64x2::ZERO))
    310    }
    311}
    312
    313/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
    314///
    315/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi32&expand=3491)
    316#[inline]
    317#[target_feature(enable = "avx512cd")]
    318#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    319#[cfg_attr(test, assert_instr(vplzcntd))]
    320#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    321pub const fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i {
    322    unsafe { transmute(simd_ctlz(a.as_i32x16())) }
    323}
    324
    325/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
    326///
    327/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi32&expand=3492)
    328#[inline]
    329#[target_feature(enable = "avx512cd")]
    330#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    331#[cfg_attr(test, assert_instr(vplzcntd))]
    332#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    333pub const fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i {
    334    unsafe {
    335        let zerocount = _mm512_lzcnt_epi32(a).as_i32x16();
    336        transmute(simd_select_bitmask(k, zerocount, src.as_i32x16()))
    337    }
    338}
    339
    340/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
    341///
    342/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi32&expand=3493)
    343#[inline]
    344#[target_feature(enable = "avx512cd")]
    345#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    346#[cfg_attr(test, assert_instr(vplzcntd))]
    347#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    348pub const fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i {
    349    unsafe {
    350        let zerocount = _mm512_lzcnt_epi32(a).as_i32x16();
    351        transmute(simd_select_bitmask(k, zerocount, i32x16::ZERO))
    352    }
    353}
    354
    355/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
    356///
    357/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi32&expand=3488)
    358#[inline]
    359#[target_feature(enable = "avx512cd,avx512vl")]
    360#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    361#[cfg_attr(test, assert_instr(vplzcntd))]
    362#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    363pub const fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i {
    364    unsafe { transmute(simd_ctlz(a.as_i32x8())) }
    365}
    366
    367/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
    368///
    369/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi32&expand=3489)
    370#[inline]
    371#[target_feature(enable = "avx512cd,avx512vl")]
    372#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    373#[cfg_attr(test, assert_instr(vplzcntd))]
    374#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    375pub const fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
    376    unsafe {
    377        let zerocount = _mm256_lzcnt_epi32(a).as_i32x8();
    378        transmute(simd_select_bitmask(k, zerocount, src.as_i32x8()))
    379    }
    380}
    381
    382/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
    383///
    384/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi32&expand=3490)
    385#[inline]
    386#[target_feature(enable = "avx512cd,avx512vl")]
    387#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    388#[cfg_attr(test, assert_instr(vplzcntd))]
    389#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    390pub const fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i {
    391    unsafe {
    392        let zerocount = _mm256_lzcnt_epi32(a).as_i32x8();
    393        transmute(simd_select_bitmask(k, zerocount, i32x8::ZERO))
    394    }
    395}
    396
    397/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst.
    398///
    399/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi32&expand=3485)
    400#[inline]
    401#[target_feature(enable = "avx512cd,avx512vl")]
    402#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    403#[cfg_attr(test, assert_instr(vplzcntd))]
    404#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    405pub const fn _mm_lzcnt_epi32(a: __m128i) -> __m128i {
    406    unsafe { transmute(simd_ctlz(a.as_i32x4())) }
    407}
    408
    409/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
    410///
    411/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi32&expand=3486)
    412#[inline]
    413#[target_feature(enable = "avx512cd,avx512vl")]
    414#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    415#[cfg_attr(test, assert_instr(vplzcntd))]
    416#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    417pub const fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
    418    unsafe {
    419        let zerocount = _mm_lzcnt_epi32(a).as_i32x4();
    420        transmute(simd_select_bitmask(k, zerocount, src.as_i32x4()))
    421    }
    422}
    423
    424/// Counts the number of leading zero bits in each packed 32-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
    425///
    426/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi32&expand=3487)
    427#[inline]
    428#[target_feature(enable = "avx512cd,avx512vl")]
    429#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    430#[cfg_attr(test, assert_instr(vplzcntd))]
    431#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    432pub const fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i {
    433    unsafe {
    434        let zerocount = _mm_lzcnt_epi32(a).as_i32x4();
    435        transmute(simd_select_bitmask(k, zerocount, i32x4::ZERO))
    436    }
    437}
    438
    439/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
    440///
    441/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi64&expand=3500)
    442#[inline]
    443#[target_feature(enable = "avx512cd")]
    444#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    445#[cfg_attr(test, assert_instr(vplzcntq))]
    446#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    447pub const fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i {
    448    unsafe { transmute(simd_ctlz(a.as_i64x8())) }
    449}
    450
    451/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
    452///
    453/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi64&expand=3501)
    454#[inline]
    455#[target_feature(enable = "avx512cd")]
    456#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    457#[cfg_attr(test, assert_instr(vplzcntq))]
    458#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    459pub const fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i {
    460    unsafe {
    461        let zerocount = _mm512_lzcnt_epi64(a).as_i64x8();
    462        transmute(simd_select_bitmask(k, zerocount, src.as_i64x8()))
    463    }
    464}
    465
    466/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
    467///
    468/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi64&expand=3502)
    469#[inline]
    470#[target_feature(enable = "avx512cd")]
    471#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    472#[cfg_attr(test, assert_instr(vplzcntq))]
    473#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    474pub const fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i {
    475    unsafe {
    476        let zerocount = _mm512_lzcnt_epi64(a).as_i64x8();
    477        transmute(simd_select_bitmask(k, zerocount, i64x8::ZERO))
    478    }
    479}
    480
    481/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
    482///
    483/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi64&expand=3497)
    484#[inline]
    485#[target_feature(enable = "avx512cd,avx512vl")]
    486#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    487#[cfg_attr(test, assert_instr(vplzcntq))]
    488#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    489pub const fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i {
    490    unsafe { transmute(simd_ctlz(a.as_i64x4())) }
    491}
    492
    493/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
    494///
    495/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi64&expand=3498)
    496#[inline]
    497#[target_feature(enable = "avx512cd,avx512vl")]
    498#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    499#[cfg_attr(test, assert_instr(vplzcntq))]
    500#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    501pub const fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i {
    502    unsafe {
    503        let zerocount = _mm256_lzcnt_epi64(a).as_i64x4();
    504        transmute(simd_select_bitmask(k, zerocount, src.as_i64x4()))
    505    }
    506}
    507
    508/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
    509///
    510/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi64&expand=3499)
    511#[inline]
    512#[target_feature(enable = "avx512cd,avx512vl")]
    513#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    514#[cfg_attr(test, assert_instr(vplzcntq))]
    515#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    516pub const fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i {
    517    unsafe {
    518        let zerocount = _mm256_lzcnt_epi64(a).as_i64x4();
    519        transmute(simd_select_bitmask(k, zerocount, i64x4::ZERO))
    520    }
    521}
    522
    523/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst.
    524///
    525/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi64&expand=3494)
    526#[inline]
    527#[target_feature(enable = "avx512cd,avx512vl")]
    528#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    529#[cfg_attr(test, assert_instr(vplzcntq))]
    530#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    531pub const fn _mm_lzcnt_epi64(a: __m128i) -> __m128i {
    532    unsafe { transmute(simd_ctlz(a.as_i64x2())) }
    533}
    534
    535/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
    536///
    537/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi64&expand=3495)
    538#[inline]
    539#[target_feature(enable = "avx512cd,avx512vl")]
    540#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    541#[cfg_attr(test, assert_instr(vplzcntq))]
    542#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    543pub const fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
    544    unsafe {
    545        let zerocount = _mm_lzcnt_epi64(a).as_i64x2();
    546        transmute(simd_select_bitmask(k, zerocount, src.as_i64x2()))
    547    }
    548}
    549
    550/// Counts the number of leading zero bits in each packed 64-bit integer in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
    551///
    552/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi64&expand=3496)
    553#[inline]
    554#[target_feature(enable = "avx512cd,avx512vl")]
    555#[stable(feature = "stdarch_x86_avx512", since = "1.89")]
    556#[cfg_attr(test, assert_instr(vplzcntq))]
    557#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
    558pub const fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i {
    559    unsafe {
    560        let zerocount = _mm_lzcnt_epi64(a).as_i64x2();
    561        transmute(simd_select_bitmask(k, zerocount, i64x2::ZERO))
    562    }
    563}
    564
    565#[allow(improper_ctypes)]
    566unsafe extern "C" {
    567    #[link_name = "llvm.x86.avx512.conflict.d.512"]
    568    fn vpconflictd(a: i32x16) -> i32x16;
    569    #[link_name = "llvm.x86.avx512.conflict.d.256"]
    570    fn vpconflictd256(a: i32x8) -> i32x8;
    571    #[link_name = "llvm.x86.avx512.conflict.d.128"]
    572    fn vpconflictd128(a: i32x4) -> i32x4;
    573
    574    #[link_name = "llvm.x86.avx512.conflict.q.512"]
    575    fn vpconflictq(a: i64x8) -> i64x8;
    576    #[link_name = "llvm.x86.avx512.conflict.q.256"]
    577    fn vpconflictq256(a: i64x4) -> i64x4;
    578    #[link_name = "llvm.x86.avx512.conflict.q.128"]
    579    fn vpconflictq128(a: i64x2) -> i64x2;
    580}
    581
    582#[cfg(test)]
    583mod tests {
    584    use crate::core_arch::assert_eq_const as assert_eq;
    585
    586    use crate::core_arch::x86::*;
    587    use stdarch_test::simd_test;
    588
    589    #[simd_test(enable = "avx512cd")]
    590    const fn test_mm512_broadcastmw_epi32() {
    591        let a: __mmask16 = 2;
    592        let r = _mm512_broadcastmw_epi32(a);
    593        let e = _mm512_set1_epi32(2);
    594        assert_eq_m512i(r, e);
    595    }
    596
    597    #[simd_test(enable = "avx512cd,avx512vl")]
    598    const fn test_mm256_broadcastmw_epi32() {
    599        let a: __mmask16 = 2;
    600        let r = _mm256_broadcastmw_epi32(a);
    601        let e = _mm256_set1_epi32(2);
    602        assert_eq_m256i(r, e);
    603    }
    604
    605    #[simd_test(enable = "avx512cd,avx512vl")]
    606    const fn test_mm_broadcastmw_epi32() {
    607        let a: __mmask16 = 2;
    608        let r = _mm_broadcastmw_epi32(a);
    609        let e = _mm_set1_epi32(2);
    610        assert_eq_m128i(r, e);
    611    }
    612
    613    #[simd_test(enable = "avx512cd")]
    614    const fn test_mm512_broadcastmb_epi64() {
    615        let a: __mmask8 = 2;
    616        let r = _mm512_broadcastmb_epi64(a);
    617        let e = _mm512_set1_epi64(2);
    618        assert_eq_m512i(r, e);
    619    }
    620
    621    #[simd_test(enable = "avx512cd,avx512vl")]
    622    const fn test_mm256_broadcastmb_epi64() {
    623        let a: __mmask8 = 2;
    624        let r = _mm256_broadcastmb_epi64(a);
    625        let e = _mm256_set1_epi64x(2);
    626        assert_eq_m256i(r, e);
    627    }
    628
    629    #[simd_test(enable = "avx512cd,avx512vl")]
    630    const fn test_mm_broadcastmb_epi64() {
    631        let a: __mmask8 = 2;
    632        let r = _mm_broadcastmb_epi64(a);
    633        let e = _mm_set1_epi64x(2);
    634        assert_eq_m128i(r, e);
    635    }
    636
    637    #[simd_test(enable = "avx512cd")]
    638    fn test_mm512_conflict_epi32() {
    639        let a = _mm512_set1_epi32(1);
    640        let r = _mm512_conflict_epi32(a);
    641        let e = _mm512_set_epi32(
    642            1 << 14
    643                | 1 << 13
    644                | 1 << 12
    645                | 1 << 11
    646                | 1 << 10
    647                | 1 << 9
    648                | 1 << 8
    649                | 1 << 7
    650                | 1 << 6
    651                | 1 << 5
    652                | 1 << 4
    653                | 1 << 3
    654                | 1 << 2
    655                | 1 << 1
    656                | 1 << 0,
    657            1 << 13
    658                | 1 << 12
    659                | 1 << 11
    660                | 1 << 10
    661                | 1 << 9
    662                | 1 << 8
    663                | 1 << 7
    664                | 1 << 6
    665                | 1 << 5
    666                | 1 << 4
    667                | 1 << 3
    668                | 1 << 2
    669                | 1 << 1
    670                | 1 << 0,
    671            1 << 12
    672                | 1 << 11
    673                | 1 << 10
    674                | 1 << 9
    675                | 1 << 8
    676                | 1 << 7
    677                | 1 << 6
    678                | 1 << 5
    679                | 1 << 4
    680                | 1 << 3
    681                | 1 << 2
    682                | 1 << 1
    683                | 1 << 0,
    684            1 << 11
    685                | 1 << 10
    686                | 1 << 9
    687                | 1 << 8
    688                | 1 << 7
    689                | 1 << 6
    690                | 1 << 5
    691                | 1 << 4
    692                | 1 << 3
    693                | 1 << 2
    694                | 1 << 1
    695                | 1 << 0,
    696            1 << 10
    697                | 1 << 9
    698                | 1 << 8
    699                | 1 << 7
    700                | 1 << 6
    701                | 1 << 5
    702                | 1 << 4
    703                | 1 << 3
    704                | 1 << 2
    705                | 1 << 1
    706                | 1 << 0,
    707            1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    708            1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    709            1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    710            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    711            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    712            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    713            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    714            1 << 2 | 1 << 1 | 1 << 0,
    715            1 << 1 | 1 << 0,
    716            1 << 0,
    717            0,
    718        );
    719        assert_eq_m512i(r, e);
    720    }
    721
    722    #[simd_test(enable = "avx512cd")]
    723    fn test_mm512_mask_conflict_epi32() {
    724        let a = _mm512_set1_epi32(1);
    725        let r = _mm512_mask_conflict_epi32(a, 0, a);
    726        assert_eq_m512i(r, a);
    727        let r = _mm512_mask_conflict_epi32(a, 0b11111111_11111111, a);
    728        let e = _mm512_set_epi32(
    729            1 << 14
    730                | 1 << 13
    731                | 1 << 12
    732                | 1 << 11
    733                | 1 << 10
    734                | 1 << 9
    735                | 1 << 8
    736                | 1 << 7
    737                | 1 << 6
    738                | 1 << 5
    739                | 1 << 4
    740                | 1 << 3
    741                | 1 << 2
    742                | 1 << 1
    743                | 1 << 0,
    744            1 << 13
    745                | 1 << 12
    746                | 1 << 11
    747                | 1 << 10
    748                | 1 << 9
    749                | 1 << 8
    750                | 1 << 7
    751                | 1 << 6
    752                | 1 << 5
    753                | 1 << 4
    754                | 1 << 3
    755                | 1 << 2
    756                | 1 << 1
    757                | 1 << 0,
    758            1 << 12
    759                | 1 << 11
    760                | 1 << 10
    761                | 1 << 9
    762                | 1 << 8
    763                | 1 << 7
    764                | 1 << 6
    765                | 1 << 5
    766                | 1 << 4
    767                | 1 << 3
    768                | 1 << 2
    769                | 1 << 1
    770                | 1 << 0,
    771            1 << 11
    772                | 1 << 10
    773                | 1 << 9
    774                | 1 << 8
    775                | 1 << 7
    776                | 1 << 6
    777                | 1 << 5
    778                | 1 << 4
    779                | 1 << 3
    780                | 1 << 2
    781                | 1 << 1
    782                | 1 << 0,
    783            1 << 10
    784                | 1 << 9
    785                | 1 << 8
    786                | 1 << 7
    787                | 1 << 6
    788                | 1 << 5
    789                | 1 << 4
    790                | 1 << 3
    791                | 1 << 2
    792                | 1 << 1
    793                | 1 << 0,
    794            1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    795            1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    796            1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    797            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    798            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    799            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    800            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    801            1 << 2 | 1 << 1 | 1 << 0,
    802            1 << 1 | 1 << 0,
    803            1 << 0,
    804            0,
    805        );
    806        assert_eq_m512i(r, e);
    807    }
    808
    809    #[simd_test(enable = "avx512cd")]
    810    fn test_mm512_maskz_conflict_epi32() {
    811        let a = _mm512_set1_epi32(1);
    812        let r = _mm512_maskz_conflict_epi32(0, a);
    813        assert_eq_m512i(r, _mm512_setzero_si512());
    814        let r = _mm512_maskz_conflict_epi32(0b11111111_11111111, a);
    815        let e = _mm512_set_epi32(
    816            1 << 14
    817                | 1 << 13
    818                | 1 << 12
    819                | 1 << 11
    820                | 1 << 10
    821                | 1 << 9
    822                | 1 << 8
    823                | 1 << 7
    824                | 1 << 6
    825                | 1 << 5
    826                | 1 << 4
    827                | 1 << 3
    828                | 1 << 2
    829                | 1 << 1
    830                | 1 << 0,
    831            1 << 13
    832                | 1 << 12
    833                | 1 << 11
    834                | 1 << 10
    835                | 1 << 9
    836                | 1 << 8
    837                | 1 << 7
    838                | 1 << 6
    839                | 1 << 5
    840                | 1 << 4
    841                | 1 << 3
    842                | 1 << 2
    843                | 1 << 1
    844                | 1 << 0,
    845            1 << 12
    846                | 1 << 11
    847                | 1 << 10
    848                | 1 << 9
    849                | 1 << 8
    850                | 1 << 7
    851                | 1 << 6
    852                | 1 << 5
    853                | 1 << 4
    854                | 1 << 3
    855                | 1 << 2
    856                | 1 << 1
    857                | 1 << 0,
    858            1 << 11
    859                | 1 << 10
    860                | 1 << 9
    861                | 1 << 8
    862                | 1 << 7
    863                | 1 << 6
    864                | 1 << 5
    865                | 1 << 4
    866                | 1 << 3
    867                | 1 << 2
    868                | 1 << 1
    869                | 1 << 0,
    870            1 << 10
    871                | 1 << 9
    872                | 1 << 8
    873                | 1 << 7
    874                | 1 << 6
    875                | 1 << 5
    876                | 1 << 4
    877                | 1 << 3
    878                | 1 << 2
    879                | 1 << 1
    880                | 1 << 0,
    881            1 << 9 | 1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    882            1 << 8 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    883            1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    884            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    885            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    886            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    887            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    888            1 << 2 | 1 << 1 | 1 << 0,
    889            1 << 1 | 1 << 0,
    890            1 << 0,
    891            0,
    892        );
    893        assert_eq_m512i(r, e);
    894    }
    895
    896    #[simd_test(enable = "avx512cd,avx512vl")]
    897    fn test_mm256_conflict_epi32() {
    898        let a = _mm256_set1_epi32(1);
    899        let r = _mm256_conflict_epi32(a);
    900        let e = _mm256_set_epi32(
    901            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    902            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    903            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    904            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    905            1 << 2 | 1 << 1 | 1 << 0,
    906            1 << 1 | 1 << 0,
    907            1 << 0,
    908            0,
    909        );
    910        assert_eq_m256i(r, e);
    911    }
    912
    913    #[simd_test(enable = "avx512cd,avx512vl")]
    914    fn test_mm256_mask_conflict_epi32() {
    915        let a = _mm256_set1_epi32(1);
    916        let r = _mm256_mask_conflict_epi32(a, 0, a);
    917        assert_eq_m256i(r, a);
    918        let r = _mm256_mask_conflict_epi32(a, 0b11111111, a);
    919        let e = _mm256_set_epi32(
    920            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    921            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    922            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    923            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    924            1 << 2 | 1 << 1 | 1 << 0,
    925            1 << 1 | 1 << 0,
    926            1 << 0,
    927            0,
    928        );
    929        assert_eq_m256i(r, e);
    930    }
    931
    932    #[simd_test(enable = "avx512cd,avx512vl")]
    933    fn test_mm256_maskz_conflict_epi32() {
    934        let a = _mm256_set1_epi32(1);
    935        let r = _mm256_maskz_conflict_epi32(0, a);
    936        assert_eq_m256i(r, _mm256_setzero_si256());
    937        let r = _mm256_maskz_conflict_epi32(0b11111111, a);
    938        let e = _mm256_set_epi32(
    939            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    940            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    941            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    942            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    943            1 << 2 | 1 << 1 | 1 << 0,
    944            1 << 1 | 1 << 0,
    945            1 << 0,
    946            0,
    947        );
    948        assert_eq_m256i(r, e);
    949    }
    950
    951    #[simd_test(enable = "avx512cd,avx512vl")]
    952    fn test_mm_conflict_epi32() {
    953        let a = _mm_set1_epi32(1);
    954        let r = _mm_conflict_epi32(a);
    955        let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
    956        assert_eq_m128i(r, e);
    957    }
    958
    959    #[simd_test(enable = "avx512cd,avx512vl")]
    960    fn test_mm_mask_conflict_epi32() {
    961        let a = _mm_set1_epi32(1);
    962        let r = _mm_mask_conflict_epi32(a, 0, a);
    963        assert_eq_m128i(r, a);
    964        let r = _mm_mask_conflict_epi32(a, 0b00001111, a);
    965        let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
    966        assert_eq_m128i(r, e);
    967    }
    968
    969    #[simd_test(enable = "avx512cd,avx512vl")]
    970    fn test_mm_maskz_conflict_epi32() {
    971        let a = _mm_set1_epi32(1);
    972        let r = _mm_maskz_conflict_epi32(0, a);
    973        assert_eq_m128i(r, _mm_setzero_si128());
    974        let r = _mm_maskz_conflict_epi32(0b00001111, a);
    975        let e = _mm_set_epi32(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
    976        assert_eq_m128i(r, e);
    977    }
    978
    979    #[simd_test(enable = "avx512cd")]
    980    fn test_mm512_conflict_epi64() {
    981        let a = _mm512_set1_epi64(1);
    982        let r = _mm512_conflict_epi64(a);
    983        let e = _mm512_set_epi64(
    984            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    985            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    986            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    987            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    988            1 << 2 | 1 << 1 | 1 << 0,
    989            1 << 1 | 1 << 0,
    990            1 << 0,
    991            0,
    992        );
    993        assert_eq_m512i(r, e);
    994    }
    995
    996    #[simd_test(enable = "avx512cd")]
    997    fn test_mm512_mask_conflict_epi64() {
    998        let a = _mm512_set1_epi64(1);
    999        let r = _mm512_mask_conflict_epi64(a, 0, a);
    1000        assert_eq_m512i(r, a);
    1001        let r = _mm512_mask_conflict_epi64(a, 0b11111111, a);
    1002        let e = _mm512_set_epi64(
    1003            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1004            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1005            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1006            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1007            1 << 2 | 1 << 1 | 1 << 0,
    1008            1 << 1 | 1 << 0,
    1009            1 << 0,
    1010            0,
    1011        );
    1012        assert_eq_m512i(r, e);
    1013    }
    1014
    1015    #[simd_test(enable = "avx512cd")]
    1016    fn test_mm512_maskz_conflict_epi64() {
    1017        let a = _mm512_set1_epi64(1);
    1018        let r = _mm512_maskz_conflict_epi64(0, a);
    1019        assert_eq_m512i(r, _mm512_setzero_si512());
    1020        let r = _mm512_maskz_conflict_epi64(0b11111111, a);
    1021        let e = _mm512_set_epi64(
    1022            1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1023            1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1024            1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1025            1 << 3 | 1 << 2 | 1 << 1 | 1 << 0,
    1026            1 << 2 | 1 << 1 | 1 << 0,
    1027            1 << 1 | 1 << 0,
    1028            1 << 0,
    1029            0,
    1030        );
    1031        assert_eq_m512i(r, e);
    1032    }
    1033
    1034    #[simd_test(enable = "avx512cd,avx512vl")]
    1035    fn test_mm256_conflict_epi64() {
    1036        let a = _mm256_set1_epi64x(1);
    1037        let r = _mm256_conflict_epi64(a);
    1038        let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
    1039        assert_eq_m256i(r, e);
    1040    }
    1041
    1042    #[simd_test(enable = "avx512cd,avx512vl")]
    1043    fn test_mm256_mask_conflict_epi64() {
    1044        let a = _mm256_set1_epi64x(1);
    1045        let r = _mm256_mask_conflict_epi64(a, 0, a);
    1046        assert_eq_m256i(r, a);
    1047        let r = _mm256_mask_conflict_epi64(a, 0b00001111, a);
    1048        let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
    1049        assert_eq_m256i(r, e);
    1050    }
    1051
    1052    #[simd_test(enable = "avx512cd,avx512vl")]
    1053    fn test_mm256_maskz_conflict_epi64() {
    1054        let a = _mm256_set1_epi64x(1);
    1055        let r = _mm256_maskz_conflict_epi64(0, a);
    1056        assert_eq_m256i(r, _mm256_setzero_si256());
    1057        let r = _mm256_maskz_conflict_epi64(0b00001111, a);
    1058        let e = _mm256_set_epi64x(1 << 2 | 1 << 1 | 1 << 0, 1 << 1 | 1 << 0, 1 << 0, 0);
    1059        assert_eq_m256i(r, e);
    1060    }
    1061
    1062    #[simd_test(enable = "avx512cd,avx512vl")]
    1063    fn test_mm_conflict_epi64() {
    1064        let a = _mm_set1_epi64x(1);
    1065        let r = _mm_conflict_epi64(a);
    1066        let e = _mm_set_epi64x(1 << 0, 0);
    1067        assert_eq_m128i(r, e);
    1068    }
    1069
    1070    #[simd_test(enable = "avx512cd,avx512vl")]
    1071    fn test_mm_mask_conflict_epi64() {
    1072        let a = _mm_set1_epi64x(1);
    1073        let r = _mm_mask_conflict_epi64(a, 0, a);
    1074        assert_eq_m128i(r, a);
    1075        let r = _mm_mask_conflict_epi64(a, 0b00000011, a);
    1076        let e = _mm_set_epi64x(1 << 0, 0);
    1077        assert_eq_m128i(r, e);
    1078    }
    1079
    1080    #[simd_test(enable = "avx512cd,avx512vl")]
    1081    fn test_mm_maskz_conflict_epi64() {
    1082        let a = _mm_set1_epi64x(1);
    1083        let r = _mm_maskz_conflict_epi64(0, a);
    1084        assert_eq_m128i(r, _mm_setzero_si128());
    1085        let r = _mm_maskz_conflict_epi64(0b00000011, a);
    1086        let e = _mm_set_epi64x(1 << 0, 0);
    1087        assert_eq_m128i(r, e);
    1088    }
    1089
    1090    #[simd_test(enable = "avx512cd")]
    1091    const fn test_mm512_lzcnt_epi32() {
    1092        let a = _mm512_set1_epi32(1);
    1093        let r = _mm512_lzcnt_epi32(a);
    1094        let e = _mm512_set1_epi32(31);
    1095        assert_eq_m512i(r, e);
    1096    }
    1097
    1098    #[simd_test(enable = "avx512cd")]
    1099    const fn test_mm512_mask_lzcnt_epi32() {
    1100        let a = _mm512_set1_epi32(1);
    1101        let r = _mm512_mask_lzcnt_epi32(a, 0, a);
    1102        assert_eq_m512i(r, a);
    1103        let r = _mm512_mask_lzcnt_epi32(a, 0b11111111_11111111, a);
    1104        let e = _mm512_set1_epi32(31);
    1105        assert_eq_m512i(r, e);
    1106    }
    1107
    1108    #[simd_test(enable = "avx512cd")]
    1109    const fn test_mm512_maskz_lzcnt_epi32() {
    1110        let a = _mm512_set1_epi32(2);
    1111        let r = _mm512_maskz_lzcnt_epi32(0, a);
    1112        assert_eq_m512i(r, _mm512_setzero_si512());
    1113        let r = _mm512_maskz_lzcnt_epi32(0b11111111_11111111, a);
    1114        let e = _mm512_set1_epi32(30);
    1115        assert_eq_m512i(r, e);
    1116    }
    1117
    1118    #[simd_test(enable = "avx512cd,avx512vl")]
    1119    const fn test_mm256_lzcnt_epi32() {
    1120        let a = _mm256_set1_epi32(1);
    1121        let r = _mm256_lzcnt_epi32(a);
    1122        let e = _mm256_set1_epi32(31);
    1123        assert_eq_m256i(r, e);
    1124    }
    1125
    1126    #[simd_test(enable = "avx512cd,avx512vl")]
    1127    const fn test_mm256_mask_lzcnt_epi32() {
    1128        let a = _mm256_set1_epi32(1);
    1129        let r = _mm256_mask_lzcnt_epi32(a, 0, a);
    1130        assert_eq_m256i(r, a);
    1131        let r = _mm256_mask_lzcnt_epi32(a, 0b11111111, a);
    1132        let e = _mm256_set1_epi32(31);
    1133        assert_eq_m256i(r, e);
    1134    }
    1135
    1136    #[simd_test(enable = "avx512cd,avx512vl")]
    1137    const fn test_mm256_maskz_lzcnt_epi32() {
    1138        let a = _mm256_set1_epi32(1);
    1139        let r = _mm256_maskz_lzcnt_epi32(0, a);
    1140        assert_eq_m256i(r, _mm256_setzero_si256());
    1141        let r = _mm256_maskz_lzcnt_epi32(0b11111111, a);
    1142        let e = _mm256_set1_epi32(31);
    1143        assert_eq_m256i(r, e);
    1144    }
    1145
    1146    #[simd_test(enable = "avx512cd,avx512vl")]
    1147    const fn test_mm_lzcnt_epi32() {
    1148        let a = _mm_set1_epi32(1);
    1149        let r = _mm_lzcnt_epi32(a);
    1150        let e = _mm_set1_epi32(31);
    1151        assert_eq_m128i(r, e);
    1152    }
    1153
    1154    #[simd_test(enable = "avx512cd,avx512vl")]
    1155    const fn test_mm_mask_lzcnt_epi32() {
    1156        let a = _mm_set1_epi32(1);
    1157        let r = _mm_mask_lzcnt_epi32(a, 0, a);
    1158        assert_eq_m128i(r, a);
    1159        let r = _mm_mask_lzcnt_epi32(a, 0b00001111, a);
    1160        let e = _mm_set1_epi32(31);
    1161        assert_eq_m128i(r, e);
    1162    }
    1163
    1164    #[simd_test(enable = "avx512cd,avx512vl")]
    1165    const fn test_mm_maskz_lzcnt_epi32() {
    1166        let a = _mm_set1_epi32(1);
    1167        let r = _mm_maskz_lzcnt_epi32(0, a);
    1168        assert_eq_m128i(r, _mm_setzero_si128());
    1169        let r = _mm_maskz_lzcnt_epi32(0b00001111, a);
    1170        let e = _mm_set1_epi32(31);
    1171        assert_eq_m128i(r, e);
    1172    }
    1173
    1174    #[simd_test(enable = "avx512cd")]
    1175    const fn test_mm512_lzcnt_epi64() {
    1176        let a = _mm512_set1_epi64(1);
    1177        let r = _mm512_lzcnt_epi64(a);
    1178        let e = _mm512_set1_epi64(63);
    1179        assert_eq_m512i(r, e);
    1180    }
    1181
    1182    #[simd_test(enable = "avx512cd")]
    1183    const fn test_mm512_mask_lzcnt_epi64() {
    1184        let a = _mm512_set1_epi64(1);
    1185        let r = _mm512_mask_lzcnt_epi64(a, 0, a);
    1186        assert_eq_m512i(r, a);
    1187        let r = _mm512_mask_lzcnt_epi64(a, 0b11111111, a);
    1188        let e = _mm512_set1_epi64(63);
    1189        assert_eq_m512i(r, e);
    1190    }
    1191
    1192    #[simd_test(enable = "avx512cd")]
    1193    const fn test_mm512_maskz_lzcnt_epi64() {
    1194        let a = _mm512_set1_epi64(2);
    1195        let r = _mm512_maskz_lzcnt_epi64(0, a);
    1196        assert_eq_m512i(r, _mm512_setzero_si512());
    1197        let r = _mm512_maskz_lzcnt_epi64(0b11111111, a);
    1198        let e = _mm512_set1_epi64(62);
    1199        assert_eq_m512i(r, e);
    1200    }
    1201
    1202    #[simd_test(enable = "avx512cd,avx512vl")]
    1203    const fn test_mm256_lzcnt_epi64() {
    1204        let a = _mm256_set1_epi64x(1);
    1205        let r = _mm256_lzcnt_epi64(a);
    1206        let e = _mm256_set1_epi64x(63);
    1207        assert_eq_m256i(r, e);
    1208    }
    1209
    1210    #[simd_test(enable = "avx512cd,avx512vl")]
    1211    const fn test_mm256_mask_lzcnt_epi64() {
    1212        let a = _mm256_set1_epi64x(1);
    1213        let r = _mm256_mask_lzcnt_epi64(a, 0, a);
    1214        assert_eq_m256i(r, a);
    1215        let r = _mm256_mask_lzcnt_epi64(a, 0b00001111, a);
    1216        let e = _mm256_set1_epi64x(63);
    1217        assert_eq_m256i(r, e);
    1218    }
    1219
    1220    #[simd_test(enable = "avx512cd,avx512vl")]
    1221    const fn test_mm256_maskz_lzcnt_epi64() {
    1222        let a = _mm256_set1_epi64x(1);
    1223        let r = _mm256_maskz_lzcnt_epi64(0, a);
    1224        assert_eq_m256i(r, _mm256_setzero_si256());
    1225        let r = _mm256_maskz_lzcnt_epi64(0b00001111, a);
    1226        let e = _mm256_set1_epi64x(63);
    1227        assert_eq_m256i(r, e);
    1228    }
    1229
    1230    #[simd_test(enable = "avx512cd,avx512vl")]
    1231    const fn test_mm_lzcnt_epi64() {
    1232        let a = _mm_set1_epi64x(1);
    1233        let r = _mm_lzcnt_epi64(a);
    1234        let e = _mm_set1_epi64x(63);
    1235        assert_eq_m128i(r, e);
    1236    }
    1237
    1238    #[simd_test(enable = "avx512cd,avx512vl")]
    1239    const fn test_mm_mask_lzcnt_epi64() {
    1240        let a = _mm_set1_epi64x(1);
    1241        let r = _mm_mask_lzcnt_epi64(a, 0, a);
    1242        assert_eq_m128i(r, a);
    1243        let r = _mm_mask_lzcnt_epi64(a, 0b00001111, a);
    1244        let e = _mm_set1_epi64x(63);
    1245        assert_eq_m128i(r, e);
    1246    }
    1247
    1248    #[simd_test(enable = "avx512cd,avx512vl")]
    1249    const fn test_mm_maskz_lzcnt_epi64() {
    1250        let a = _mm_set1_epi64x(1);
    1251        let r = _mm_maskz_lzcnt_epi64(0, a);
    1252        assert_eq_m128i(r, _mm_setzero_si128());
    1253        let r = _mm_maskz_lzcnt_epi64(0b00001111, a);
    1254        let e = _mm_set1_epi64x(63);
    1255        assert_eq_m128i(r, e);
    1256    }
    1257}